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cplds at fpga densities? delta39k? isr? cpld family preliminary cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-03039 rev. ** revised april 4, 2001 features high density ? 15k to 350k usable gates ? 256 to 5376 macrocells ? 92 to 520 maximum i/o pins ? 12 dedicated inputs including 4 clock pins, 4 global control signal pins and 4 jtag interface pins for reconfigurability embedded memory ? 40k to 840k bits embedded sram 32k to 672k bits of (single port) cluster memory 8k to 168k bits of (dual port) channel memory high speed - 250-mhz in-system operation anyvolt ? interface ? 3.3v, 2.5v and 1.8v v cc versions available ? 3.3v, 2.5v and 1.8v i/o capability on all versions low power operation ? 0.18- m 6-layer metal sram-based logic process ? full-cmos implementation of product term array ? standby current as low as 100 a at 1.8v v cc simple timing model ? no penalty for using full 16 product terms / macrocell ? no delay for single product term steering or sharing flexible clocking ? 4 synchronous clocks per device ? 1 spread-aware pll drives all 4 clock networks ? locally generated product term clock ? clock polarity control at each register carry-chain logic for fast and efficient arithmetic opera- tions multiple i/o standards supported ? lvcmos (3.3/3.0/2.5/1.8v), lvttl, 3.3v pci, sstl2 (i-ii), sstl3 (i-ii), hstl (i-iv), and gtl+ compatible with nobl ? , zbt ? , and qdr ? srams programmable slew rate control on each i/o pin user-programmable bus hold capability on each i/o pin fully pci compliant (to 66 mhz 64-bit pci spec rev2.2) compact pci hot swap compatible multiple package/pinout offering across all densities ? 144 to 676 pins in pqfp, bga and fbga packages ? same pinout for 3.3v/2.5v and 1.8v devices ? simplifies design migration across density ? self-boot ? solution in bga and fbga packages in-system reprogrammable ? (isr ? ) ? jtag-compliant on-board programming ? design changes don ? t cause pinout changes ieee1149.1 jtag boundary scan development software warp ? ? ieee 1076/1164 vhdl or ieee 1364 verilog context sensitive editing. ? active-hdl fsm graphical finite state machine editor ? active-hdl sim post-synthesis timing simulator ? architecture explorer for detailed design analysis ? static timing analyzer for critical path analysis ? available on windows 95, 98 & nt for $99 ? supports all cypress programmable logic products note: 1. upper limit of typical gates is calculated by assuming only 10% of the channel memory is used. 2. standby i cc values are with pll not utilized, no output load and stable inputs delta39k ? isr cpld family members device typical gates [1] macrocells cluster memory (kbits) channel memory (kbits) maximum i/o pins f max2 (mhz) speed - t pd pin-to-pin (ns) standby i cc [2] t a =25 c 3.3/2.5v 1.8v 39k15 8k ? 24k 256 32 8 134 256 6.5 10 ma 100 a 39k30 16k ? 48k 512 64 16 176 238 7.0 10 ma 200 a 39k50 23k ? 72k 768 96 24 218 238 7.0 10 ma 300 a 39k100 46k ? 144k 1536 192 48 302 222 7.5 10 ma 600 a 39k165 77k ? 241k 2560 320 80 386 181 8.5 10 ma 1250 a 39k200 92k ? 288k 3072 384 96 428 181 8.5 10 ma 1250 a 39k250 115k ? 361k 3840 480 120 470 167 8.5 10 ma 1500 a 39k350 161k ? 505k 5376 672 168 520 154 9.0 10 ma 2100 a
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 2 of 57 delta39k speed bins [3] device 250 222 200 181 167 154 125 83 39k15 x xx 39k30 x x x 39k50 x x x 39k100 x x x 39k165 x x x 39k200 x x x 39k250 x x x 39k350 xxx device package offering and i/o count including dedicated clock and control inputs device 208-eqfp 28x28 mm 0.5-mm pitch 144-fbga 13x13 mm 1.0-mm pitch 256-fbga 17x17 mm 1.0-mm pitch 484-fbga 23x23 mm 1.0-mm pitch 676-fbga 27x27 mm 1.0-mm pitch self-boot solution [4] 256-fbga 17x17 mm 1.0-mm pitch 388-bga 35x35 mm 1.27-mm pitch 484-fbga 23x23 mm 1.0-mm pitch 676-fbga 27x27 mm 1.0-mm pitch 39k15 134 92 134 134 39k30 136 92 176 176 39k50 136 180 218 218 39k100 136 180 302 294 302 39k165 136 356 294 386 39k200 136 368 294 428 39k250 136 470 294 470 39k350 136 520 294 520 notes: 3. speed bins shown here are for commercial operating range. please refer to delta39k ordering information on page 41 for indust rial range speed bins. 4. self-boot solution integrates the boot prom (flash memory) with delta39k die inside the same package.
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 3 of 57 figure 1. delta39k100 block diagram (3 rows x 4 columns) with i/o bank structure 4 gclk[3:0] 4 4 4 channel ram 4 gclk[3:0] 4 4 4 4 gclk[3:0] 4 4 4 4 4 gclk[3:0] pll & clock mux gctl[3:0] i/o bank 6 i/o bank 7 i/o bank 3 i/o bank 2 i/o bank 4 i/o bank 5 i/o bank 1 i/o bank 0 lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 4 of 57 general description the delta39k family, based on a 0.18 m , 6-layer metal cmos logic process, offers a wide range of high-density solu- tions at unparalleled system performance. the delta39k fam- ily is designed to combine the high speed, predictable timing, and ease of use of cplds with the high densities and low power of fpgas. with devices ranging from 15,000 to 350,000 usable gates, the family features devices ten times the size of previously available cplds. even at these large densities, the delta39k family is fast enough to implement a fully synthesiz- able 64-bit, 66-mhz pci core. the architecture is based on logic block clusters (lbc) that are connected by horizontal and vertical (h&v) routing chan- nels. each lbc features eight individual logic blocks (lb) and two cluster memory blocks. adjacent to each lbc is a channel memory block, which can be accessed directly from the i/o pins. both types of memory blocks are highly configurable and can be cascaded in width and depth. see figure 1 for a block diagram of the delta39k architecture. all the members of the delta39k family have cypress ? s highly regarded in-system reprogrammability (isr) feature, which simplifies both design and manufacturing flows, thereby re- ducing costs. the isr feature provides the ability to reconfig- ure the devices without having design changes cause pinout or timing changes in most cases. the cypress isr function is implemented through a jtag-compliant serial interface. data is shifted in and out through the tdi and tdo pins respective- ly. superior routability, simple timing, and the isr allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance. the entire family features jtag for isr and boundary scan, and is compatible with the pci local bus specification, meet- ing the electrical and timing requirements. the delta39k fam- ily also features user programmable bus-hold and slew rate control capabilities on each i/o pin. anyvolt interface all delta39kv devices feature an on-chip regulator, which ac- cepts 3.3v or 2.5v on the v cc supply pins and steps it down to 1.8v internally, the voltage level at which the core operates. the delta39kz devices accept 1.8v on the v cc supply pins directly. with delta39k ? s anyvolt technology, the i/o pins can be connected to either 1.8v, 2.5v, or 3.3v. all delta39k devic- es are 3.3v tolerant regardless of v ccio or v cc settings. global routing description the routing architecture of the delta39k is made up of hori- zontal and vertical (h&v) routing channels. these routing channels allow signals from each of the delta39k architectural components to communicate with one another. in addition to the horizontal and vertical routing channels that interconnect the i/o banks, channel memory blocks, and logic block clus- ters, each lbc contains a programmable interconnect matrix (pim ? ), which is used to route signals among the logic blocks and the cluster memory blocks. figure 2 is a block diagram of the routing channels that inter- face within the delta39k architecture. the lbc is exactly the same for every member of the delta39k cpld family. logic block cluster (lbc) the delta39k architecture consists of several logic block clus- ters, each of which have 8 logic blocks (lb) and 2 cluster memory blocks connected via a programmable interconnect matrix (pim) as shown in figure 3 . each cluster memory block consists of 8-kbit single-port ram, which is configurable as synchronous or asynchronous. the cluster memory blocks can be cascaded with other cluster memory blocks within the same lbc as well as other lbcs to implement larger memory functions. if a cluster memory block is not specifically utilized by the designer, cypress ? s warp software can automatically use it to implement large blocks of logic. all lbcs interface with each other via horizontal and vertical routing channels. note: 5. for hstl only. device v cc v ccio 39kv 3.3v or 2.5v 3.3v or 2.5v or 1.8v or 1.5v [5] 39kz 1.8v 3.3v or 2.5v or 1.8v or 1.5v [5] figure 2. delta39k routing interface lb cluster pim cluster memory block lb lb lb lb cluster memory block lb lb lb channel memory block i/o block i/o block channel memory outputs drive dedicated tracks in the horizontal and vertical routing channels h-to-v pim v-to-h pim pin inputs from the i/o cells drive dedicated tracks in the horizontal and vertical routing channels 72 72 64 64
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 5 of 57 logic block (lb) the logic block is the basic building block of the delta39k ar- chitecture. it consists of a product term array, an intelligent product-term allocator, and 16 macrocells. product term array each logic block features a 72 x 83 programmable product term array. this array accepts 36 inputs from the pim. these inputs originate from device pins and macrocell feedbacks as well as cluster memory and channel memory feedbacks. ac- tive low and active high versions of each of these inputs are generated to create the full 72-input field. the 83 product terms in the array can be created from any of the 72 inputs. of the 83 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. two of the remaining three product terms in the logic block are used as asynchronous set and asynchronous reset product terms. the final product term is the product term clock (ptclk) and is shared by all 16 macrocells within a logic block. product term allocator through the product term allocator, warp software automati- cally distributes the 80 product terms as needed among the 16 macrocells in the logic block. the product term allocator pro- vides two important capabilities without affecting performance: product term steering and product term sharing. product term steering product term steering is the process of assigning product terms to macrocells as needed. for example, if one macrocell requires ten product terms while another needs just three, the product term allocator will ? steer ? ten product terms to one macrocell and three to the other. on delta39k devices, prod- uct terms are steered on an individual basis. any number be- tween 1and 16 product terms can be steered to any macrocell. product term sharing product term sharing is the process of using the same product term among multiple macrocells. for example, if more than one function has one or more product terms in its equation that are common to other functions, those product terms are only programmed once. the delta39k product term allocator al- lows sharing across groups of four macrocells in a variable fashion. the software automatically takes advantage of this capability so that the user does not have to intervene. note that neither product term sharing nor product term steer- ing have any effect on the speed of the product. all steering and sharing configurations have been incorporated in the tim- ing specifications for the delta39k devices. . figure 3. delta39k logic block cluster diagram logic block 0 logic block 1 logic block 3 logic block 2 cluster memory 0 pim logic block 7 logic block 6 logic block 4 logic block 5 cluster memory 1 64 inputs from horizontal routing channel 64 inputs from vertical routing channel 144 outputs to horizontal and vertical cluster-to-channel pims clock inputs gclk[3:0] cc cc cc cc cc cc cc = carry chain 16 36 16 36 16 36 16 36 16 36 16 36 16 36 8 25 8 25 4 16 36
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 6 of 57 macrocell within each logic block there are 16 macrocells. each macrocell accepts a sum of up to 16 product terms from the product term array. the sum of these 16 product terms can be output in either registered or combinatorial mode. figure 4 displays the block diagram of the macrocell. the register can be asynchronously preset or asynchronously reset at the mac- rocell level with the separate preset and reset product terms. each of these product terms features programmable polarity. this allows the registers to be preset or reset based on an and expression or an or expression. an xor gate in the delta39k macrocell allows for many differ- ent types of equations to be realized. it can be used as a po- larity mux to implement the true or complement form of an equation in the product term array or as a toggle to turn the d flip-flop into a t flip-flop. the carry-chain input mux allows ad- ditional flexibility for the implementation of different types of logic. the macrocell can utilize the carry chain logic to imple- ment adders, subtractors, magnitude comparators, parity tree, or even generic xor logic. the output of the macrocell is ei- ther registered or combinatorial. carry chain logic the delta39k macrocell features carry chain logic which is used for fast and efficient implementation of arithmetic opera- tions. the carry logic connects macrocells in up to 4 logic blocks for a total of 64 macrocells. effective data path opera- tions are implemented through the use of carry-in arithmetic, which drives through the circuit quickly. figure 4 shows that the carry chain logic within the macrocell consists of two prod- uct terms (cpt0 and cpt1) from the pta and an input carry- in for carry logic. the inputs to the carry chain mux are con- nected directly to the product terms in the pta. the output of the carry chain mux generates the carry-out for the next mac- rocell in the logic block as well as the local carry input that is connected to an input of the xor input mux. carry-in and a configuration bit are inputs to an and gate. this and gate provides a method of segmenting the carry chain in any mac- rocell in the logic block. macrocell clocks clocking of the register is highly flexible. four global synchro- nous clocks (gclk[3:0]) and a product term clock (ptclk) are available at each macrocell register. furthermore, a clock polarity mux within each macrocell allows the register to be clocked on the rising or the falling edge (see macrocell dia- gram in figure 4 ). preset/reset configurations the macrocell register can be asynchronously preset and re- set using the preset and reset mux. both signals are ac- tive high and can be controlled by either of two preset/reset product terms (prc[1:0] in figure 4 ) or gnd. in situations where the preset and reset are active at the same time, reset takes priority over preset. figure 4. delta39k macrocell d q pset res gclk[3:0] ptclk from ptm cpt0 cpt1 prc[1:0] 0 1 0 1 to pim c carry out (to macrocell n+1) carry in (from macrocell n-1) up to 16 pts preset mux clock polarity mux reset mux clock mux carry chain mux xor input mux output mux q c 3 3 2 3 c c c c c c
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 7 of 57 embedded memory each member of the delta39k family contains two types of embedded memory blocks. the channel memory block is placed at the intersection of horizontal and vertical routing channels. each channel memory block is 4096 bits in size and can be configured as asynchronous or synchronous dual-port ram, single-port ram, read-only memory (rom), or syn- chronous fifo memory. the memory organization is config- urable as 4kx1, 2kx2, 1kx4 and 512x8. the second type of memory block is located within each lbc and is referred to as a cluster memory block. each lbc contains two cluster mem- ory blocks that are 8192-bits in size. similar to the channel memory blocks, the cluster memory blocks can be configured as 8kx1, 4kx2, 2kx4 and 1kx8 asynchronous or synchronous single-port ram or rom. cluster memory each logic block cluster of the delta39k contains two 8192-bit cluster memory blocks. figure 5 is a block diagram of the clus- ter memory block and the interface of the cluster memory block to the cluster pim. the output of the cluster memory block can be optionally reg- istered to perform synchronous pipelining or to register asyn- chronous read and write operations. the output registers con- tain an asynchronous reset which can be used in any type of sequential logic circuits (e.g., state machines). there are four global clocks (gclk[3:0]) and one local clock available for the input and the output registers. the local clock for the input registers is independent of the one used for the output registers. the local clock is generated in the user-de- sign in a macrocell or comes from an i/o pin. cluster memory initialization the cluster memory powers up in an undefined state, but is set to a user-defined known state during configuration. to fa- cilitate the use of look-up-table (lut) logic and rom applica- tions, the cluster memory blocks can be initialized with a given set of data when the device is configured at power up. for lut and rom applications, the user cannot write to memory blocks. channel memory the delta39k architecture includes an embedded memory block at each crossing point of horizontal and vertical routing channels. the channel memory is a 4096-bit embedded mem- ory block that can be configured as asynchronous or synchro- nous single-port ram, dual-port ram, rom, or synchronous fifo memory. data, address, and control inputs to the channel memory are driven from horizontal and vertical routing channels. all data and fifo logic outputs drive dedicated tracks in the horizontal and vertical routing channels. the clocks for the channel mem- ory block are selected from four global clocks and pin inputs from the horizontal and vertical channels. the clock muxes also include a polarity mux for each clock so that the user can choose an inverted clock. dual-port (channel memory) configuration each port has distinct address inputs, as well as separate data and control inputs that can be accessed simultaneously. the inputs to the dual-port memory are driven from the horizontal and vertical routing channels. the data outputs drive dedicat- ed tracks in the routing channels. the interface to the routing is such that port a of the dual-port interfaces primarily with the horizontal routing channel and port b interfaces primarily with the vertical routing channel. . figure 5. block diagram of cluster memory block 5:1 din[7:0] dq addr[12:0] dq cluster pim dq we write pulse write control logic 1024x8 asynchronous sram read control logic row decode (1024 rows) dout[7:0] 8 3 3 8 10 c c d q gclk[3:0] 5:1 r reset gclk[3:0] c local clk 2 local clk 3 2 3 c c c c c c c
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 8 of 57 the clocks for each port of the dual-port configuration are selected from four global clocks and two local clocks. one lo- cal clock is sourced from the horizontal channel and the other from the vertical channel. the data outputs of the dual-port memory can also be registered. clocks for the output registers are also selected from four global clocks and two local clocks. one clock polarity mux per port allows the use of true or com- plement polarity for input and output clocking purposes. arbitration the dual-port configuration of the channel memory block pro- vides arbitration when both ports access the same address at the same time. depending on the memory operation being at- tempted, one port always gets priority. see table 1 for details on which port gets priority for read and write operations. an active-low ? address match ? signal is generated when an ad- dress collision occurs. fifo (channel memory) configuration the channel memory blocks are also configurable as synchro- nous fifo ram. in the fifo mode of operation, the channel memory block supports all normal fifo operations without the use of any general-purpose logic resources in the device. the fifo block contains all of the necessary fifo flag logic, including the read and write address pointers. the fifo flags include an empty/full flag (ef ), half-full flag (hf ), and program- mable almost-empty/full (paef ) flag output. the fifo config- uration has the ability to perform simultaneous read and write operations using two separate clocks. these clocks may be tied together for a single operation or may run independently for asynchronous read/write (w.r.t. each other) applications. the data and control inputs to the fifo block are driven from the horizontal or vertical routing channels. the data and flag outputs are driven onto dedicated routing tracks in both the horizontal and vertical routing channels. this allows the fifo blocks to be expanded by using multiple fifo blocks on the same horizontal or vertical routing channel without any speed penalty. in fifo mode, the write and read ports are controlled by sep- arate clock and enable signals. the clocks for each port are selected from four global clocks and two local clocks. one local clock is sourced from the horizontal channel and the other from the vertical channel. the data outputs from the read port of the fifo can also be registered. one clock polarity mux per port allows using true or complement polarity for read and write operations. the write operation is controlled by the clock and the write enable pin. the read operation is controlled by the clock and the read enable pin. the enable pins can be sourced from horizontal or vertical channels. table 1. arbitration result: address match signal becomes active port a port b result of arbitration comment read read no arbitration required both ports read at the same time write read port a gets priority if port b requests first then it will read the cur- rent data. the output will then change to the newly written data by port a read write port b gets priority if port a requests first then it will read the cur- rent data. the output will then change to the newly written data by port b write write port a gets priority port b is blocked until port a is finished writing figure 6. block diagram of channel memory block 4096-bit dual port array configurable as async/sync dual port or sync fifo configurable as 4kx1, 2kx2, 1kx4 and 512x8 block sizes horizontal channel all channel memory inputs are driven from the routing channels all channel memory outputs drive dedicated tracks in the routing channels gclk[3:0] global clock signals vertical channel
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 9 of 57 channel memory initialization the channel memory powers up in an undefined state, but is set to a user-defined known state during configuration. to fa- cilitate the use of look-up-table (lut) logic and rom applica- tions, the channel memory blocks can be initialized with a giv- en set of data when the device is configured at power up. for lut and rom applications, the user cannot write to memory blocks. channel memory routing interface similar to lbc outputs, the channel memory blocks feature dedicated tracks in the horizontal and vertical routing channels for the data outputs and the flag outputs, as shown in figure 6 . this allows the channel memory blocks to be ex- panded easily. these dedicated lines can be routed to i/o pins as chip outputs or to other logic block clusters to be used in logic equations. i/o banks the delta39k interfaces the horizontal and vertical routing channels to the pins through i/o banks. there are 8 i/o banks per device as shown in figure 7 , and all i/os from an i/o bank are located in the same section of a package for pcb layout convenience. for each package type, delta39k devices of different densities keep given pins in the same i/o banks. this supports and sim- plifies design migration across densities. each i/o bank contains several i/o cells, and each i/o cell contains an input/output register, an output enable register, programmable slew rate control and programmable bus hold control logic. each i/o cell drives a pin output of the device; the cell also supplies an input to the device that connects to a dedicated track in the associated routing channel. there are four dedicated inputs (gctl[3:0]) that are used as global control signals available to every i/o cell. these global control signals may be used as output enables, register resets and register clock enables as shown in figure 8 . each i/o bank can use any supported i/o standard by supply- ing appropriate v ref and v ccio voltages. all the v ref and v ccio pins in an i/o bank must be connected to the same v ref and v ccio voltage respectively. this requirement restricts the number of i/o standards supported by an i/o bank at any given time. the number of i/os which can be used in each i/o bank de- pend on the type of i/o standards and the number of v ccio and gnd pins being used. this restriction is derived from the electromigration limit of the v ccio and gnd bussing on the chip. please refer to the note on page 17 and the application note titled ? delta39k family device i/o standards and config- urations ? for details. figure 7. delta39k i/o bank block diagram i/o standards i/o standard v ref (v) v ccio termination voltage (v tt ) min. max. lvttl n/a 3.3v n/a lvcmos 3.3v n/a lvcmos3 3.0v n/a lvcmos2 2.5v n/a lvcmos18 1.8v n/a 3.3v pci 3.3v n/a gtl+ 0.9 1.1 n/a 1.5 sstl3 i 1.3 1.7 3.3v 1.5 sstl3 ii 1.3 1.7 3.3v 1.5 sstl2 i 1.15 1.35 2.5v 1.25 sstl2 ii 1.15 1.35 2.5v 1.25 hstl i 0.68 0.9 1.5v 0.75 hstl ii 0.68 0.9 1.5v 0.75 hstl iii 0.68 0.9 1.5v 1.5 hstl iv 0.68 0.9 1.5v 1.5 delta39k bank 0 bank 1 bank 4 bank 5 bank 2 bank 3 bank 6 bank 7 delta39k
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 10 of 57 . i/o cell figure 8 is a block diagram of the delta39k i/o cell. the i/o cell contains a three-state input buffer, an output buffer, and a register that can be configured as an input or output register. the output buffer has a slew rate control option that can be used to configure the output for a slower slew rate. the input of the device and the pin output can each be configured as registered or combinatorial; however, only one path can be configured as registered in a given design. the output enable can be selected from one of the four global control signals or from one of two output control channel (occ) signals. the output enable can be configured as always enabled or always disabled or it can be controlled by one of the remaining inputs to the mux. the selection is done via a mux that includes v cc and gnd as inputs. one of the global clocks can be selected as the clock for the i/o cell register. the clock mux output is an input to a clock polarity mux that allows the input/output register to be clocked on either edge of the clock. slew rate control the ouput buffer has a slew rate control option. this allows the output buffer to slew at a fast rate (3 v/ns) or a slow rate (1 v/ns). all i/os default to fast slew rate. for designs concerned with meeting fcc emissions standards the slow edge pro- vides for lower system noise. for designs requiring very high performance the fast edge rate provides maximum system performance. programmable bus hold on each i/o pin, user-programmable-bus-hold is included. bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device ? s performance. as a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in bus-in- terface applications. bus-hold additionally allows unused de- vice pins to remain unconnected on the board, which is partic- ularly useful during prototyping as designers can route new signals to the device without cutting trace connections to v cc or gnd. for more information, see the application note ? un- derstanding bus-hold ? a feature of cypress cplds. ? clocks delta39k has four dedicated clock input pins (gclk[3:0]) to accept system clocks. one of these clocks (gclk[0]) may be selected to drive an on-chip phase-locked loop (pll) for fre- quency modulation (see figure 9 for details). the global clock tree for a delta39k device can be driven by a combination of the dedicated clock pins and/or the pll-de- rived clocks. the global clock tree consists of four global clocks that go to every macrocell, memory block, and i/o cell. clock tree distribution the global clock tree performs two primary functions. first, the clock tree generates the four global clocks by multiplexing four dedicated clocks from the package pins and four pll driven clocks. second, the clock tree distributes the four global clocks to every cluster, channel memory, and i/o block on the die. the global clock tree is designed such that the clock skew is minimized while maintaining an acceptable clock delay. figure 8. block diagram of i/o cell dq res e global control signals output control channel occ global clock signals slew rate control c i/o from output pim to routing channel oe mux register input mux register enable mux output mux clock mux clock polarity mux register reset mux input mux bus hold c dq res c registered oe mux c c c 3 c 3 c 2 3 c c c
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 11 of 57 spread aware ? pll each device in the delta39k family features an on-chip pll designed using spread aware technology for low emi applica- tions. in general, plls are used to implement time-division- multiplex circuits to achieve higher performance with fewer de- vice resources. for example, a system that operates on a 32-bit data path that runs at 40 mhz can be implemented with 16-bit circuitry that runs internally at 80 mhz. plls can also be used to take ad- vantage of the positioning of the internally generated clock edges to shift performance towards improved setup, hold or clock-to-out times. there are several frequency multiply (x1, x2, x4) and divide (/1, /2, /3, /4, /5, /6. /8, /16) options available to create a wide range of clock frequencies from a single clock input (gclk[0]). for increased flexibility, there are seven phase shifting options which allow clock skew/de-skew by 45 , 90 , 135 , 180 , 225 , 270 or 315 . the voltage controlled oscillator (vco), the core of the delta39k pll is designed to operate within the frequency range of 100 mhz to 266 mhz. hence, the multiply option com- bined with input (gclk[0]) frequency should be selected such that this vco operating frequency requirement is met. this is demonstrated in table 2 (columns 1, 2, and 3). another feature of this pll is the ability to drive the output clock (intclk) off the delta39k chip to clock other devices on the board, as shown in figure 9 above. this off-chip clock is half the frequency of the output clock as it has to go through a register (i/o register or a macrocell register). this pll can also be used for board de-skewing purpose by driving a pll output clock off-chip, routing it to the other de- vices on the board and feeding it back to the pll ? s external feedback input (gclk[1]). when this feature is used, only lim- ited multiply, divide and phase shift options can be used. table 2 describes the valid multiply and divide options that can be used without an external feedback. table 3 describes the valid multiply & divide options that can be used with an exter- nal feedback. gclk[3:0] gclk0 gclk1 fb source clock clock tree delay lock pll x1, x2, x4 gclk0 gclk1 gclk2 intclk0 intclk1 intclk2 normal i/o signal path lock detect/io pin any register intclk0, intclk1, intclk2, intclk3 send a global clock off chip c c c c c c clk 0 0 clk 90 0 clk 180 0 clk 270 0 clk 225 0 clk 135 0 clk 45 0 clk 315 0 divide gclk3 intclk3 2 2 2 2 2 fb off-chip signal (external feedback) phase selection phase selection phase selection phase selection 1-6,8,16 divide 1-6,8,16 divide 1-6,8,16 divide 1-6,8,16 figure 9. block diagram of spread aware pll table 2. pll multiply and divide options ? without external feedback input frequency (gclk[0]) f plli (mhz) valid multiply options valid divide options value vco output frequency (mhz) value output frequency (intclk[3:0]) f pllo (mhz) off-chip clock frequency 25 ? 33 4 100 ? 133 1 ? 6, 8, 16 6.25 ? 133 3.12 ? 66 33 ? 50 4 133 ? 200 1 ? 6, 8, 16 8.33 ? 200 4.16 ? 100 50 ? 66 4200 ? 266 1 ? 6, 8, 16 12.5 ? 266 6.25 ? 133 2100 ? 133 1 ? 6, 8, 16 6.25 ? 133 3.12 ? 66 66 ? 100 2 133 ? 200 1 ? 6, 8, 16 8.3 ? 200 4.16 ? 100 100 ? 133 2200 ? 266 1 ? 6, 8, 16 12.5 ? 266 6.25 ? 133 1100 ? 133 1 ? 6, 8, 16 6.25 ? 133 3.12 ? 66
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 12 of 57 table 4 describes the valid phase shift options that can be used with or without an external feedback. table 5 is an example of the effect of all the available divide and phase shift options on a vco output of 250 mhz. it also shows the effect of division on the duty cycle of the resultant clock. note that the duty cycle is 50-50 when a vco output is divided by an even number. also note that the phase shift ap- plies to the vco output and not to the divided output. the spread aware pll operates as specified for delta39kv devices (2.5v/3.3v), but not delta39kz devices (1.8v). for more details on the architecture and operation of this pll please refer to the application note entitled ? delta39k pll and clock tree. ? table 3. pll multiply and divide options ? with external feedback input (gclk) frequency f plli (mhz) valid multiply options valid divide options value vco output frequency (mhz) value output (intclk) frequency f pllo (mhz) off-chip clock frequency 50 ? 66 1 100 ? 133 1 100 ? 133 50 ? 66 66 ? 100 1 133 ? 200 1 133 ? 200 66 ? 100 100 ? 133 1 200 ? 266 1 200 ? 266 100 ? 133 table 4. pll phase shift options ? with and without external feedback without external feedback with external feedback 0 ,45 , 90 , 135 , 180 , 225 , 270 , 315 0 table 5. timing of clock phases for all divide options for a vco output frequency of 250 mhz divide factor period (ns) duty cy- cle% 0 (ns) 45 (ns) 90 (ns) 135 (ns) 180 (ns) 225 (ns) 270 (ns) 315 (ns) 1 4 40-60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2 8 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3 12 33-67 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4 16 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5 20 40-60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 6 24 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 8 32 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 16 64 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 13 of 57 timing model one important feature of the delta39k family is the simplicity of its timing. all combinatorial and registered/synchronous de- lays are worst case and system performance is static (as shown in the ac specs section) as long as data is routed through the same horizontal and vertical channels. figure 10 illustrates the true timing model for the 200-mhz devices. for synchronous clocking of macrocells, a delay is incurred from macrocell clock to macrocell clock of separate logic blocks within the same cluster, as well as separate logic blocks with- in different clusters. this is respectively shown as t scs and t scs2 in figure 10. for combinatorial paths, any input to any output (from corner to corner on the device), incurs a worst- case delay in the 39k100 regardless of the amount of logic or which horizontal and vertical channels are used. this is the t pd shown in figure 10. for synchronous systems, the input set- up time to the output macrocell register and the clock to output time are shown as the parameters t mcs and t mcco shown in the figure 10. these measurements are for any output and synchronous clock, regardless of the logic placement. the delta39k features: no dedicated vs. i/o pin delays no penalty for using 0 ? 16 product terms no added delay for steering product terms no added delay for sharing product terms no output bypass delays the simple timing model of the delta39k family eliminates un- expected performance penalties. figure 10. timing model for 39k100 device channel ram 4 gclk[3:0] lb 0 pim ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim 8 kb sram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 8 kb sram channel ram 4 gclk[3:0] lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram 4 lb 0 pim ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 gclk[3:0] lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram channel ram cluster cluster cluster t mcs t pd t scs t mcco t scs2
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 14 of 57 ieee 1149.1 compliant jtag operation the delta39k family has an ieee 1149.1 jtag interface for both boundary scan and isr operations. four dedicated pins are reserved on each device for use by the test access port (tap). boundary scan the delta39k family supports bypass, sample/preload, ex- test, intest, idcode and usercode boundary scan instructions. the jtag interface is shown in figure 11 . in-system reprogramming (isr) in-system reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. this combination means design changes during debug or field upgrades do not cause board respins. the delta39k family implements isr by providing a jtag compliant interface for on-board programming, robust routing resources for pinout flexibility, and a simple timing model for consistent system performance. configuration each device of the delta39k family is available in a volatile and a self-boot package. cypress ? s cpld boot eeprom is used to store configuration data for the volatile solution and an em- bedded on-chip flash memory device is used for the self- boot solution. for volatile delta39k packages, programming is defined as the loading of a user ? s design into the external cpld boot eeprom. for self-boot delta39k packages, programming is defined as the loading of a user ? s design into the on-chip flash internal to the delta39k package. configuration is de- fined as the loading of a user ? s design into the delta39k die. configuration can begin in two ways. it can be initiated by tog- gling the reconfig pin from low to high, or by issuing the appropriate ieee std 1149.1 jtag instruction to the delta39k device via the jtag interface. there are two ieee std 1149.1 jtag instructions that initiate configuration of the delta39k. the self config instruction causes the delta39k to (re)config- ure with data stored in the serial boot prom or the embedded flash memory. the load config instruction causes the delta39k to (re)configure according to data provided by other sources such as a pc, automatic test equipment (ate), or an embedded micro-controller/processor via the jtag interface. for more information on configuring delta39k devices, refer to the application note titled ? configuring delta39k/quantum38k ? application note at http://www.cypress.com. there are two configuration options available for issuing the ieee std 1149.1 jtag instructions to the delta39k. the first method is to use a pc with the c3isr programming cable and software. with this method, the isr pins of the delta39k de- vices in the system are routed to a connector at the edge of the printed circuit board. the c3isr programming cable is then connected between the pc and this connector. a simple configuration file instructs the isr software of the program- ming operations to be performed on the delta39k devices in the system. the isr software then automatically completes all of the necessary data manipulations required to accomplish configuration, reading, verifying, and other isr functions. for more information on the cypress isr interface, see the isr programming kit data sheet (cy3900i). the second configuration option for the delta39k is to utilize the embedded controller or processor that already exists in the system. the delta39k isr software assists in this method by converting the device hex file into the isr serial stream that contains the isr instruction information and the addresses and data of locations to be configured. the embedded control- ler then simply directs this isr stream to the chain of delta39k devices to complete the desired reconfiguration or diagnostic operations. contact your local sales office for information on availability of this option. programming the on-chip flash device of the delta39k self-boot package is programmed by issuing the appropriate ieee std 1149.1 jtag instruction to the internal flash memory via the jtag interface. this can be done automatically using isr/stapl software. the configuration bits are sent from a pc through the jtag port into the delta39k via the c3isr programming cable. the data is then internally passed from delta39k to the on-chip flash. for more information on how to program the delta39k through isr/stapl, please refer to the isr/stapl user guide. the external cpld boot eeprom used to store configuration data for the delta39k volatile package is programmed through cypress ? s cydh2200e cpld boot prom programming kit via a two-wire interface. for more information on how to pro- gram the cpld boot eeprom, please refer to the data sheet titled ? cydh2200e cpld boot prom programming kit. ? for more information on the architecture and timing specification of the boot eeprom, refer to the data sheet titled ? cpld boot eeprom. ? third-party programmers cypress support is available on a wide variety of third-party programmers. all major programmers (including bp micro, system general, hi-lo) support the delta39k family. development software support warp warp is a state-of-the-art design environment for designing with cypress programmable logic. warp utilizes a subset of figure 11. jtag interface instruction register boundary scan idcode usercode isr prog. bypass reg. data registers jtag tap controller tdo tdi tms tclk
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 15 of 57 ieee 1076/1164 vhdl and ieee 1364 as the hardware de- scription language (hdl) for design entry. warp accepts vhdl or verilog input, synthesizes and optimizes the entered design, and outputs a configuration bitstream for the desired delta39k device. for simulation, warp provides a graphical waveform simulator as well as vhdl and verilog timing mod- els. vhdl and verilog are open, powerful, non-proprietary hard- ware description languages (hdls) that are standards for be- havioral design entry and simulation. hdl allows designers to learn a single language that is useful for all facets of the design process. third-party software cypress products are supported in a number of third-party de- sign entry and simulation tools. refer to the third-party soft- ware data sheet or contact your local sales office for a list of currently supported third party vendors.
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 16 of 57 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .................................. ? 65 c to +150 c soldering temperature...................................................220 c ambient temperature with power applied............................................... ? 40 c to +85 c junction temperature....................................................135 c v cc to ground potential (39kz device)......... .. ? 0.5v to 2.5v v cc to ground potential (39kv device) ........... ? 0.5v to 4.6v v ccio to ground potential................................ ? 0.5v to 4.6v dc voltage applied to outputs in high z state ? 0.5v to 4.5v dc input voltage......................... ...................... ? 0.5v to 4.5v dc current into outputs......................................................... ...................20 ma [6] static discharge voltage (per mil-std-8883, method 3015)..............................................................>2001v latch-up current.......................................................>200 ma notes: 6. dc current into outputs is 36 ma with hstl iii, 48 ma with hstl iv and 36 ma with gtl+ (with 25 ? pull-up resistor and v tt = 1.5 7. not more than one output should be tested at a time. duration of the short circuit should not exceed 1 second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation. tested initially and after any design or process changes that may affect these pa rameters. operating range range ambient temperature junction temperature output condition v ccio v cc v ccjtag / v cccnfg v ccpll v ccprg commercial 0 c to +70 c 0 c to +85 c 3.3v 3.3v 0.3v 3.3v 0.3v or 2.5v 0.2v (39kv) 1.8v 0.15v (39kz) same as v ccio same as v cc 3.3v 0.3v 2.5v 2.5v 0.2v 1.8v 1.8v 0.15v 1.5v 1.5v 0.1v [5] industrial ? 40 c to +85 c ? 40 c to +100 c 3.3v 3.3v 0.3v 2.5v 2.5v 0.2v 1.8v 1.8v 0.15v 1.5v 1.5v 0.1v [5] dc characteristics parameter description test conditions v ccio = 3.3 v v ccio = 2.5 v v ccio = 1.8 v unit min. max. min. max. min. max. v drint data retention v cc voltage (config data may be lost below this) 1.5 1.5 1.5 v v drio data retention v ccio voltage (config data may be lost below this) 1.2 1.2 1.2 v i ix input leakage current gnd v i 3.6v ? 10 10 ? 10 10 ? 10 10 a i oz output leakage current gnd v o v ccio ? 10 10 ? 10 10 ? 10 10 a i os [7] output short circuit current v ccio = max., v out = 0.5v ? 160 ? 160 ? 160 ma i bhl input bus hold low sustaining current v cc = min., v pin = v il +40 +30 +25 a i bhh input bus hold high sustaining current v cc = min., v pin = v ih ? 40 ? 30 ? 25 a i bhlo input bus hold low overdrive current v cc = max. +250 +200 +150 a i bhho input bus hold high overdrive current v cc = max. ? 250 ? 200 ? 150 a
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 17 of 57 notes: 8. pci spec (rev 2.2) requires the idsel pin to have capacitance less than or equal to 8 pf. document titled ? delta39k pin tables ? identifies all the i/o pins, in a given package, which can be used as idsel in a pci design. all other i/o pins meet the pci requirement of capacitance less than or equal to 10 pf. 9. the number of i/os which can be used in each i/o bank depends on the type of i/o standards and the number of v ccio and gnd pins being used. please refer to the application note titled ? delta39k family device i/o standards and configurations ? for details. the source current limit per i/o bank per vccio pin is 165 ma the sink current limit per i/o bank per gnd pin is 230 ma 10. see ? power-up sequence requirements ? below for v ccio requirement. 11. 25 ? resistor terminated to termination voltage of 1.5v. capacitance parameter description test conditions min. max. unit c i/o input/output capacitance v in =v ccio @ f=1 mhz 25 c 10 pf c clk clock signal capacitance v in =v ccio @ f=1 mhz 25 c 5 12 pf c pci pci compliant [8] capacitance v in =v ccio @ f=1 mhz 25 c 8 pf dc characteristics (io) [9] input/ output standard v ref (v) v ccio (v) v oh (v) v ol (v) v ih (v) v il (v) min. max. @ i oh =v oh (min.) @ i ol = v ol (max.) min. max. min. max. lvttl n/a 3.3 ? 4 ma 2.4 4 ma 0.4 2.0 v v ccio +0.3 ? 0.3v 0.8v lvcmos 3.3 ? 0.1 ma v ccio ? 0.2v 0.1 ma 0.2 2.0 v v ccio +0.3 ? 0.3v 0.8v lvcmos3 3.0 ? 0.1 ma v ccio ? 0.2v 0.1ma 0.2 2.0 v v ccio +0.3 ? 0.3v 0.8v lvcmos2 2.5 ? 0.1 ma 2.1 0.1 ma 0.2 1.7 v v ccio +0.3 ? 0.3v 0.7v ? 1.0 ma 2.0 1.0 ma 0.4 ? 2.0 ma 1.7 2.0 ma 0.7 lvcmos18 1.8 ? 0.1 ma v ccio ? 0.2v 0.1ma 0.2 0.65v ccio v ccio +0.3 ? 0.3v 0.35v ccio ? 2 ma v ccio ? 0.45v 2.0 ma 0.45 3.3v pci 3.3 ? 0.5 ma 0.9v ccio 1.5 ma 0.1v ccio 0.5v ccio v ccio +0.5 ? 0.5v 0.3v ccio gtl+ 0.9 1.1 note 10 note 11 0.6 v ref +0.2 v ref ? 0.2 sstl3 i 1.3 1.7 3.3 ? 8 ma v ccio ? 1.1v 8 ma 0.7 v ref +0.2 v ccio +0.3 ? 0.3v v ref ? 0.2 sstl3 ii 1.3 1.7 3.3 ? 16 ma v ccio ? 0.9v 16 ma 0.5 v ref +0.2 v ccio +0.3 ? 0.3v v ref ? 0.2 sstl2 i 1.15 1.35 2.5 ? 7.6 ma v ccio ? 0.62v 7.6 ma 0.54 v ref +1.8 v ccio +0.3 ? 0.3v v ref ? 0.18 sstl2 ii 1.15 1.35 2.5 ? 15.2 ma v ccio ? 0.43v 15.2 ma 0.35 v ref +1.8 v ccio +0.3 ? 0.3v v ref ? 0.18 hstl i 0.68 0.9 1.5 ? 8 ma v ccio ? 0.4v 8 ma 0.4 v ref +1.0 v ccio +0.3 ? 0.3v v ref ? 0.1 hstl ii 0.68 0.9 1.5 ? 16 ma v ccio ? 0.4v 16 ma 0.4 v ref +1.0 v ccio +0.3 ? 0.3v v ref ? 0.1 hstl iii 0.68 0.9 1.5 ? 8 ma v ccio ? 0.4v 24 ma 0.4 v ref +1.0 v ccio +0.3 ? 0.3v v ref ? 0.1 hstl iv 0.68 0.9 1.5 ? 8 ma v ccio ? 0.4v 48 ma 0.4 v ref +1.0 v ccio +0.3 ? 0.3v v ref ? 0.1
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 18 of 57 power-up sequence requirements upon power-up, all the outputs remain three-stated until all the v cc pins have powered-up to the nominal voltage and the part has completed configuration. the part will not start configuration until v cc , v ccio , v ccjtag , v cccnfg , v ccpll and v ccprg have reached nominal voltage. v cc pins can be powered up in any order. this includes v cc , v ccio , v ccjtag , v cccnfg , v ccpll and v ccprg . all v ccio s on a bank should be tied to the same potential and powered up together. all v ccio s (even the unused banks) need to be powered up to at least 1.5v before configuration has completed. maximum ramp time for all v cc s should be 0v to nominal voltage in 100 ms. configuration parameters parameter description min. unit t reconfig reconfig pin low time before it goes high 200 ns
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 19 of 57 switching characteristics - parameter descriptions over the operating range [12] parameter description combinatorial mode parameters t pd delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the horizontal or vertical channel associated with that cluster t ea global control to output enable t er global control to output disable t prr asynchronous macrocell reset or preset recovery time from any pin input on the horizontal or vertical channel associated with the cluster the macrocell is in t pro asynchronous macrocell reset or preset from any pin input on the horizontal or vertical channel associated with the cluster that the macrocell is in to any pin output on those same channels t prw asynchronous macrocell reset or preset minimum pulse width, from any pin input to a macrocell in the farthest cluster on the horizontal or vertical channel the pin is associated with synchronous clocking parameters t mcs set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock t mch hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock t mcco global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the cluster that macrocell is in t ios set-up time of any input pin to the i/o cell register associated with that pin, relative to a global clock t ioh hold time of any input pin to the i/o cell register associated with that pin, relative to a global clock t ioco clock to output of an i/o cell register to the output pin associated with that register t scs macrocell clock to macrocell clock through array logic within the same cluster t scs2 macrocell clock to macrocell clock through array logic in different clusters on the same channel t ics i/o register clock to any macrocell clock in a cluster on the channel the i/o register is associated with t ocs macrocell clock to any i/o register clock on the horizontal or vertical channel associated with the cluster that the macrocell is in t chz clock to output disable (high-impedance) t clz clock to output enable (low-impedance) f max maximum frequency with internal feedback ? within the same cluster f max2 maximum frequency with internal feedback ? within different clusters at the opposite ends of a horizontal or vertical channel product term clock t mcspt set-up time for macrocell used as input register, from input to product term clock t mchpt hold time of macrocell used as an input register t mccopt product term clock to output delay from input pin t scs2pt register to register delay through array logic in different clusters on the same channel using a product term clock channel interconnect parameters t chsw adder for a signal to switch from a horizontal to vertical channel and vice-versa t cl2cl cluster to cluster delay adder (through channels and channel pim) note: 12. add t chsw to signals making a horizontal to vertical channel switch or vice-versa.
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 20 of 57 miscellaneous delays t cpld delay from the input of a cluster pim, through a macrocell in the cluster, back to a cluster pim input. this parameter can be added to the t pd and t scs parameters for each extra pass through the and/or array required by a given signal path t mccd adder for carry chain logic per macrocell t iod delay from the input of the output buffer to the i/o pin t ioin delay from the i/o pin to the input of the channel buffer t ckin delay from the clock pin to the input of the clock driver t ioregpin delay from the i/o pin to the input of the i/o register pll parameters t mccj maximum cycle to cycle jitter time t dwsa pll delay with skew adjustment t dwosa pll delay without any skew adjustment t lock lock time for the pll f pllo output frequency of the pll f plli input frequency of the pll jtag parameters t jckh tclk high time t jckl tclk low time t jcp tclk clock period t jsu jtag port setup time (tdi/tms inputs) t jh jtag port hold time (tdi/tms inputs) t jco jtag port clock to output time (tdo) t jxz jtag port valid output to high impedance (tdo) t jzx jtag port high impedance to valid output (tdo) switching characteristics - parameter descriptions over the operating range [12] (continued) parameter description
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 21 of 57 cluster memory timing parameter descriptions over the operating range parameter description asynchronous mode parameters t clmaa cluster memory access time. delay from address change to read data out t clmpwe write enable pulse width t clmsa address set-up to the beginning of write enable with both signals from the same i/o block t clmha address hold after the end of write enable with both signals from the same i/o block t clmsd data set-up to the end of write enable t clmhd data hold after the end of write enable synchronous mode parameters t clmcyc1 clock cycle time for flow through read and write operations (from macrocell register through cluster memory back to a macrocell register in the same cluster) t clmcyc2 clock cycle time for pipelined read and write operations (from cluster memory input register through the memory to cluster memory output register) t clms address, data, and we set-up time of pin inputs, relative to a global clock t clmh address, data, and we hold time of pin inputs, relative to a global clock t clmdv1 global clock to data valid on output pins for flow through data t clmdv2 global clock to data valid on output pins for pipelined data t clmmacs1 cluster memory input clock to macrocell clock in the same cluster t clmmacs2 cluster memory output clock to macrocell clock in the same cluster t macclms1 macrocell clock to cluster memory input clock in the same cluster t macclms2 macrocell clock to cluster memory output clock in the same cluster internal parameters t clmclaa asynchronous cluster memory access time from input of cluster memory to output of cluster memory
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 22 of 57 channel memory timing parameter descriptions over the operating range parameter description dual port asynchronous mode parameters t chmaa channel memory access time. delay from address change to read data out t chmpwe write enable pulse width t chmsa address set-up to the beginning of write enable with both signals from the same i/o block t chmha address hold after the end of write enable with both signals from the same i/o block t chmsd data set-up to the end of write enable t chmhd data hold after the end of write enable t chmba channel memory asynchronous dual port address match (busy access time) dual port synchronous mode parameters t chmcyc1 clock cycle time for flow through read and write operations (from macrocell register through channel memory back to a macrocell register in the same cluster) t chmcyc2 clock cycle time for pipelined read and write operations (from channel memory input register through the memory to channel memory output register) t chms address, data, and we set-up time of pin inputs, relative to a global clock t chmh address, data, and we hold time of pin inputs, relative to a global clock t chmdv1 global clock to data valid on output pins for flow through data t chmdv2 global clock to data valid on output pins for pipelined data. t chmbdv channel memory synchronous dual-port address match (busy, clock to data valid) t chmmacs1 channel memory input clock to macrocell clock in the same cluster t chmmacs2 channel memory output clock to macrocell clock in the same cluster t macchms1 macrocell clock to channel memory input clock in the same cluster t macchms2 macrocell clock to channel memory output clock in the same cluster synchronous fifo data parameters t chmclk read and write minimum clock cycle time t chmfs data, read enable, and write enable set-up time relative to pin inputs t chmfh data, read enable, and write enable hold time relative to pin inputs t chmfrdv data access time to output pins from rising edge of read clock (read clock to data valid) t chmmacs channel memory fifo read clock to macrocell clock for read data t macchms macrocell clock to channel memory fifo write clock for write data synchronous fifo flag parameters t chmfo read or write clock to respective flag output at output pins t chmmacf read or write clock to macrocell clock with fifo flag t chmfrs master reset pulse width t chmfrsr master reset recovery time t chmfrsf master reset to flag and data output time t chmskew1 read/write clock skew time for full flag t chmskew2 read/write clock skew time for empty flag t chmskew3 read/write clock skew time for boundary flags internal parameters t chmchaa asynchronous channel memory access time from input of channel memory to output of channel memory
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 23 of 57 switching characteristics - parameter values over the operating range parameter 250 222 200 181 167 154 125 83 min. max. min. max. min. max. min. max. min. max. min. max. min. max. min. max. unit combinatorial mode parameters t pd 6.5 7.0 7.5 8.5 8.5 9.0 10 15 ns t ea 4.0 4.5 5.0 5.6 6.5 7.5 9.0 10 ns t er 4.0 4.5 5.0 5.3 6.5 7.5 9.0 10 ns t prr 6.0 6.0 6.0 6.0 6.0 7.0 8.0 10 ns t pro 9.0 9.5 10 10.5 11 12 13 15 ns t prw 3.0 3.3 3.6 4.0 4.5 5.0 6.0 7.0 ns synchronous clocking parameters t mcs 2.5 2.7 3.0 3.5 3.5 4.0 5.0 6.0 ns t mch 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns t mcco 5.0 5.5 6.0 7.0 7.5 8.5 10 12 ns t ios 0.8 0.9 1.0 1.2 1.4 1.7 2.0 2.5 ns t ioh 0.8 0.9 1.0 1.2 1.4 1.7 2.0 2.5 ns t ioco 3.2 3.6 4.0 4.5 5.0 6.0 7.0 8.0 ns t scs 3.0 3.2 3.5 3.6 3.7 3.9 6.4 9.6 ns t scs2 3.9 4.2 4.5 5.5 5.7 6.2 8.0 12 ns t ics 4.0 4.5 5.0 5.5 6.0 6.5 8.0 12 ns t ocs 4.0 4.5 5.0 5.5 6.0 6.5 8.0 12 ns t chz 3.5 3.5 3.5 3.8 4.0 4.4 6.0 7.0 ns t clz 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns f max 333 313 286 278 270 256 156 104 mhz f max2 256 238 222 181 167 154 125 83 mhz product term clocking parameters t mcspt 2.5 2.7 3.0 3.3 3.5 4.0 5.0 6.0 ns t mchpt 0.8 0.9 1.0 1.4 1.4 1.7 2.0 2.5 ns t mccopt 7.0 7.5 8.0 8.8 9.0 10.0 11.0 15.0 ns t scs2pt 5.5 6.0 6.5 7.2 7.5 9.0 10.0 15.0 ns channel interconnect parameters t chsw 0.8 0.9 1.0 1.2 1.2 1.4 1.7 2.0 ns t cl2cl 1.6 1.8 2.0 2.3 2.4 2.6 2.8 3.0 ns miscellaneous parameters t cpld 2.5 2.8 3.0 3.3 3.5 3.8 4.0 5.0 ns t mccd 0.2 0.22 0.25 0.28 0.30 0.32 0.35 0.38 ns pll parameters t mccj 0.45 0.48 0.50 0.50 0.55 0.58 0.60 0.65 ns t dwsa 320 330 350 350 390 400 420 460 ps t dwosa 320 330 350 350 390 400 420 460 ps t lock 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 ms
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 24 of 57 f pllo [13] 6.2 266 6.2 266 6.2 266 6.2 266 6.2 266 6.2 266 6.2 200 6.2 200 mhz f plli [13] 25 133 25 133 25 133 25 133 25 133 25 133 25 100 25 100 mhz jtag parameters t jckh 25 25 25 25 25 25 25 25 ns t jckl 25 25 25 25 25 25 25 25 ns t jcp 50 50 50 50 50 50 50 50 ns t jsu 10 10 10 10 10 10 10 10 ns t jh 10 10 10 10 10 10 10 10 ns t jco 20 20 20 20 20 20 20 20 ns t jxz 20 20 20 20 20 20 20 20 ns t jzx 20 20 20 20 20 20 20 20 ns note: 13. refer to page 11 and the application note titled ? delta39k pll and clock tree ? for details on the pll operation & specification switching characteristics - parameter values over the operating range (continued) parameter 250 222 200 181 167 154 125 83 min. max. min. max. min. max. min. max. min. max. min. max. min. max. min. max. unit
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 25 of 57 input & output standard timing delay adjustments all the timing specifications in this data sheet are specified based on 3.3v pci compliant inputs and outputs (fast slew rates) . [14] apply following adjustments if the inputs and outputs are configured to operate at other standards. input/output standard output delay adjustments input delay adjustments t iod t ea t er t ioin t ckin t ioregpin lvttl ? 2 ma 2.6 0 0 0 0 0 lvttl ? 4 ma 2.0 0 0 0 0 0 lvttl ? 6 ma 2.0 0 0 0 0 0 lvttl ? 8 ma 1.2 0 0 0 0 0 lvttl ? 12 ma 1.0 0 0 0 0 0 lvttl ? 16 ma 0.5 0 0 0 0 0 lvttl ? 24 ma 0.2 0 0 0 0 0 lvcmos0.200000 lvcmos3 0.3 0.05 0 0.1 0.1 0.2 lvcmos2 0.5 0.1 0 0.2 0.2 0.4 lvcmos18 2.1 0.7 0.1 0.5 0.4 0.3 3.3v pci000000 gtl+ 0.6 [15] 0.6 [15] 0.9 [15] 0.5 0.4 0.2 sstl3 i ? 0.3 0.3 0.1 0.5 0.3 0.3 sstl3 ii ? 0.4 0.2 0 0.5 0.3 0.3 sstl2 i ? 0.1 0.4 0 0.9 0.5 0.6 sstl2 ii ? 0.2 0.2 0 0.9 0.5 0.6 hstl i 0.6 0.9 0.5 0.5 0.5 0.3 hstl ii 0.4 0.8 0.5 0.5 0.5 0.3 hstl iii 0.6 0.5 0.1 0.5 0.5 0.3 hstl iv 0.7 0.6 0 0.5 0.5 0.3 notes: 14. for ? slow slew rate ? output delay adjustments, refer to warp software ? s static timing analyzer results. 15. these delays are based on falling edge output. the rising edge delay depends on the size of pull up resistor and termination voltage.
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 26 of 57 cluster memory timing parameter values over the operating range 250 222 200 181 167 154 125 83 parameter min. max. min. max. min. max. min. max. min. max. min. max. min. max. min. max. unit asynchronous mode parameters t clmaa 9 1011121315 17 20 ns t clmpwe 55.566.57 8 10 12 ns t clmsa 1.6 1.8 2.0 2.2 2.5 2.8 3.2 4.0 ns t clmha 0.8 0.9 1.0 1.1 1.2 1.5 1.8 2.0 ns t clmsd 5.0 5.5 6.0 6.5 7.0 8.0 10 12 ns t clmhd 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ns synchronous mode parameters t clmcyc1 9.0 9.5 10 10.5 11 13 15 20 ns t clmcyc2 4.0 4.5 5.0 5.5 6.0 7.0 8.0 10.0 ns t clms 2.5 2.7 3.0 3.8 3.5 3.8 4.0 5.0 ns t clmh 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns t clmdv1 9.01011121315 17 20 ns t clmdv2 6.5 7.0 7.5 8.0 8.5 9.0 10 15 ns t clmmacs1 7.0 7.5 8.0 8.5 9.0 10 12 15 ns t clmmacs2 4.0 4.5 5.0 5.5 6.0 7.0 8.0 10 ns t macclms1 3.2 3.6 4.0 4.4 4.8 5.5 6.6 8.0 ns t macclms2 5.5 6.0 6.5 7.0 7.5 8.5 10 12 ns internal parameters t clmclaa 55.566.57 8 10 12 ns
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 27 of 57 channel memory timing parameter values 250 222 200 181 167 154 125 83 unit parameter min.max.min.max.min.max.min.max.min.max.min.max.min.max. min. max. dual-port asynchronous mode parameters t chmaa 9 1011121315 17 20 ns t chmpwe 5.0 5.5 6.0 6.5 7.0 8.0 10 12 ns t chmsa 1.6 1.8 2.0 2.2 2.5 2.8 3.2 4.0 ns t chmha 0.8 0.9 1.0 1.1 1.2 1.5 1.8 2.0 ns t chmsd 5.0 5.5 6.0 6.5 7.0 8.0 10 12 ns t chmhd 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ns t chmba 8.0 8.5 9.0 10.0 11.0 12.0 14.0 16.0 ns dual-port synchronous mode parameters t chmcyc1 9.0 9.5 10 10 11 13 15 20 ns t chmcyc2 4.2 4.6 5.0 5.4 5.8 6.2 7.4 10.6 ns t chms 2.7 3.0 3.3 3.9 4.0 4.5 5.0 6.0 ns t chmh 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns t chmdv1 9.01011121315 17 20 ns t chmdv2 6.5 7.0 7.5 8.0 8.5 9.0 10 15 ns t chmbdv 8.0 8.5 9.0 10.0 11.0 12.0 14.0 16.0 ns t chmmacs1 8.0 8.5 9.0 10.0 11.0 12.0 14.0 16.0 ns t chmmacs2 4.0 4.5 5.0 5.5 6.0 7.0 8.0 10 ns t macchms1 4.2 4.6 5.0 5.4 5.8 6.5 7.6 9.0 ns t macchms2 6.0 6.5 7.0 7.7 8.0 9.0 10.0 13.0 ns synchronous fifo data parameters t chmclk 4.2 4.6 5.0 5.4 5.8 6.2 7.4 10.6 ns t chmfs 3.5 3.7 4.0 4.3 4.5 5.0 6.0 7.0 ns t chmfh 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns t chmfrdv 6.0 6.5 7.0 7.5 8.0 9.0 10.0 13.0 t chmmacs 4.2 4.6 5.0 5.4 5.8 6.2 7.4 10.6 ns t macchms 4.2 4.6 5.0 5.4 5.8 6.2 7.4 10.6 ns synchronous fifo flag parameters t chmfo 10.0 10.5 11 11.5 12 13 15 20 ns t chmmacf 8.0 8.5 9 9.5 10 11 13 17 ns t chmfrs 4.0 4.5 5.0 5.5 6.0 7.0 8.0 10 ns t chmfrsr 3.2 3.6 4.0 4.4 4.8 5.5 6.6 8.0 ns t chmfrsf 9.0 9.5 10.0 11.0 12.0 13.0 15.0 18.0 ns t chmskew1 1.6 1.8 2.0 2.2 2.4 2.6 3.2 4.0 ns t chmskew2 1.6 1.8 2.0 2.2 2.4 2.6 3.2 4.0 ns t chmskew3 4.2 4.6 5.0 5.4 5.8 6.2 7.4 10.6 ns internal parameters t chmchaa 6.0 6.5 7.0 7.5 8.0 9.0 10.0 13.0 ns
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 28 of 57 switching waveforms t pd input combinatorial output combinatorial output delta39k-1 registered output with synchronous clocking (macrocell) t mcs input synchronous t mcco registered output t mch clock delta39k-2 registered input in i/o cell t ios data input input register clock t ioco registered output t ioh delta39k-3
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 29 of 57 switching waveforms (continued) clock to clock input register clock macrocell register clock t scs t ics delta39k-4 pt clock to pt clock data pt clock t scs2pt t mcspt delta39k-5 input asynchronous reset/preset input t pro registered output clock t prr t prw delta39k-6 reset/preset output enable/disable global control t er outputs t ea delta39k-7 input
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 30 of 57 switching waveforms (continued) cluster memory asynchronous timing address (at read write read write enable t clmpwe input output t clmclaa t clmclaa cluster memory asynchronous timing 2 address (at the read write read write enable t clmpwe input t clmsd t clmhd output t clmsa t clmha t clmaa t clmaa the cluster input) i/o pin) delta39k-8 delta39k-9
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 31 of 57 switching waveforms (continued) cluster memory synchronous flow through timing global address write enable registered input registered output t clms t clms t clms t clmh t clmh t clmh read write read t clmdv1 t clmdv1 t clmdv1 clock delta39k-10 t clmcyc1 cluster memory internal clocking macrocell cluster memory input clock cluster memory output clock t clmmacs2 t macclms2 t clmmacs1 t macclms1 delta39k-11 input clock
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 32 of 57 switching waveforms (continued) cluster memory output register timing (asynchronous inputs) address t clmcyc2 t clmdv2 write enable input global clock (output register) egistered output delta39k-12 cluster memory output register timing (synchronous inputs) address t clmdv2 write enable global clock (output register) registered output (input register) global clock t clmcyc2 delta39k-13 t clms t clmh input
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 33 of 57 switching waveforms (continued) channel memory dp asynchronous timing write t chmpwe t chmsa t chmha t chmaa t chmhd address data output t chmaa delta39k-14 a n-1 a n a n+1 a n+2 d n d n-1 d n d n+1 t chmsd enable input channel memory internal clocking clock input clock output clock t chmmacs1 t macchms2 t chmmacs2 t macchms1 delta39k-15 macrocell input channel memory channel memory
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 34 of 57 switching waveforms (continued) channel memory internal clocking 2 macrocell input clock fifo read clock fifo write clock fifo read or write clock t chmmacs t chmmacf t macchms delta39k-16 channel memory dp sram flow through r/w timing clock t chmcyc1 t chmh t chms write d n+1 t chms t chmh output a n+1 a n+2 a n+3 a n delta39k-17 address t chmdv1 t chmdv1 t chmdv1 d n-1 d n+3 d n-1 a n-1 data t chmdv1 d n+3 d n+2 d n+1 d n enable input
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 35 of 57 switching waveforms (continued) channel memory dp sram pipeline r/w timing a n+1 a n+2 d n+1 t chmcyc2 t chmh t chms t chms t chmh a n t chms t chmh delta38k-18 a n+3 a n-1 d n+3 d n-1 d n-1 t chmdv2 t chmdv2 d n d n+1 d n+2 t chmdv2 clock write output address data enable input dual-port asynchronous address match busy signal address a a n a n-1 a n a n+1 address t chmba t chmba b n address b delta39k-19 match
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 36 of 57 switching waveforms (continued) clock a n a n b n-1 b n+1 t chmbdv a n-1 t chmbdv t chms t chms address b address dual-port synchronous address match busy signal address a delta39k-20 match
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 37 of 57 switching waveforms (continued) channel memory synchronous fifo empty/write timing write enable t chmclk t chmfs t chmfh d n+1 registered input empty flag port a clock read enable t chmskew2 t chmfo t chmfo t chmfrdv port b clock re registered output delta39k-21 (active low)
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 38 of 57 switching waveforms (continued) channel memory synchronous fifo full/read timing port a clock read enable t chmclk t chmfs registered output full flag port b clock t chmfh t chmskew1 t chmfo t chmfo write enable t chms t chmh t chmfrdv registered input delta39k-22 (active low)
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 39 of 57 switching waveforms (continued) channel memory synchronous fifo programmable flag timing t chmclk t chmfs t chmfh port b clock programmable write enable almost-empty flag port a clock t chmskew3 t chmfo t chmfo read enable delta39k-23 (active low) t chmfs t chmfh t chmclk port b clock programmable write enable almost-full flag port a clock t chmskew3 t chmfo t chmfo read enable (active low)
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 40 of 57 switching waveforms (continued) channel memory synchronous fifo master reset timing master reset input read enable / write enable empty/full t chmfrs t chmfrsr t chmfrsf t chmfrsf t chmfrsf half-full/ registered output delta39k-24 flags programmable flags almost full programmable almost empty
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 41 of 57 delta39k pin table please refer to document titled ? delta39k pin tables ? for pinouts of all the packages of all delta39k family members. you can access this document on the internet at: http://www.cypress.com/pld/datasheets.html. pin count 144 = 144 balls 208 = 208 leads 256 = 256 balls 388 = 388 balls 484 = 484 balls 676 = 676 balls c y 3 9 1 0 0 v 6 7 6 - 2 0 0 m b c cypress semiconductor id family type 39 = delta39k family gate density 15=15k usable gates 165=165k usable gates 30=30k usable gates 200=200k usable gates 50=50k usable gates 250=250k usable gates 100=100k usable gates 350=350k usable gates speed 250 = 250 mhz 167 = 167 mhz 222 = 222 mhz 154 = 154 mhz 200 = 200 mh 125 = 125 mhz 181 = 181 mhz 83 = 83 mhz package type n = plastic quad flat pack (pqfp) nt = thermally enhanced quad flat pack (eqfp) bg = ball grid array (bga) bb = fine-pitch ball grid array (fbga) 1.0-mm lead pitch mg = self-boot solution - ball grid array mb = self-boot solution - fine pitch ball grid array 1.0-mm lead pitch operating conditions commercial 0 c to +70 c industrial -40 c to +85 c operating reference voltage v = 3.3v or 2.5v supply voltage z = 1.8v supply voltage delta39k part numbers [16] (ordering information) device speed (mhz) ordering code package name package type self-boot solution operating range 39k15 250 cy39015v208-250ntc nt208 208-lead enhanced quad flat pack commercial cy39015z208-250nc n208 208-lead plastic quad flat pack cy39015v144-250bbc bb144 144-lead fine pitch ball grid array cy39015z144-250bbc bb144 144-lead fine pitch ball grid array cy39015v256-250bbc bb256 256-lead fine pitch ball grid array cy39015z256-250bbc bb256 256-lead fine pitch ball grid array cy39015v256-250mbc mb256 256-lead fine pitch ball grid array cy39015z256-250mbc mb256 256-lead fine pitch ball grid array 125 cy39015v208-125ntc nt208 208-lead enhanced quad flat pack cy39015z208-125nc n208 208-lead plastic quad flat pack cy39015v144-125bbc bb144 144-lead fine pitch ball grid array cy39015z144-125bbc bb144 144-lead fine pitch ball grid array cy39015v256-125bbc bb256 256-lead fine pitch ball grid array cy39015z256-125bbc bb256 256-lead fine pitch ball grid array cy39015v256-125mbc mb256 256-lead fine pitch ball grid array cy39015z256-125mbc mb256 256-lead fine pitch ball grid array
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 42 of 57 39k15 125 cy39015v208-125nti nt208 208-lead enhanced quad flat pack industrial cy39015z208-125ni n208 208-lead plastic quad flat pack cy39015v144-125bbi bb144 144-lead fine pitch ball grid array cy39015z144-125bbi bb144 144-lead fine pitch ball grid array cy39015v256-125bbi bb256 256-lead fine pitch ball grid array cy39015z256-125bbi bb256 256-lead fine pitch ball grid array cy39015v256-125mbi mb256 256-lead fine pitch ball grid array cy39015z256-125mbi mb256 256-lead fine pitch ball grid array 83 cy39015v208-83ntc nt208 208-lead enhanced quad flat pack commercial cy39015z208-83nc n208 208-lead plastic quad flat pack cy39015v144-83bbc bb144 144-lead fine pitch ball grid array cy39015z144-83bbc bb144 144-lead fine pitch ball grid array cy39015v256-83bbc bb256 256-lead fine pitch ball grid array cy39015z256-83bbc bb256 256-lead fine pitch ball grid array cy39015v256-83mbc mb256 256-lead fine pitch ball grid array cy39015z256-83mbc mb256 256-lead fine pitch ball grid array cy39015v208-83nti nt208 208-lead plastic quad flat pack industrial cy39015z208-83ni n208 208-lead enhanced quad flat pack cy39015v144-83bbi bb144 144-lead fine pitch ball grid array cy39015z144-83bbi bb144 144-lead fine pitch ball grid array cy39015v256-83bbi bb256 256-lead fine pitch ball grid array cy39015z256-83bbi bb256 256-lead fine pitch ball grid array cy39015v256-83mbi mb256 256-lead fine pitch ball grid array cy39015z256-83mbi mb256 256-lead fine pitch ball grid array 39k30 222 cy39030v208-222ntc nt208 208-lead enhanced quad flat pack commercial cy39030z208-222nc n208 208-lead plastic quad flat pack cy39030v144-222bbc bb144 144-lead fine pitch ball grid array cy39030z144-222bbc bb144 144-lead fine pitch ball grid array cy39030v256-222bbc bb256 256-lead fine pitch ball grid array cy39030z256-222bbc bb256 256-lead fine pitch ball grid array cy39030v256-222mbc mb256 256-lead fine pitch ball grid array cy39030z256-222mbc mb256 256-lead fine pitch ball grid array 125 cy39030v208-125ntc nt208 208-lead enhanced quad flat pack cy39030z208-125nc n208 208-lead plastic quad flat pack cy39030v144-125bbc bb144 144-lead fine pitch ball grid array cy39030z144-125bbc bb144 144-lead fine pitch ball grid array cy39030v256-125bbc bb256 256-lead fine pitch ball grid array cy39030z256-125bbc bb256 256-lead fine pitch ball grid array cy39030v256-125mbc mb256 256-lead fine pitch ball grid array cy39030z256-125mbc mb256 256-lead fine pitch ball grid array delta39k part numbers [16] (ordering information) (continued) device speed (mhz) ordering code package name package type self-boot solution operating range
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 43 of 57 39k30 125 cy39030v208-125nti nt208 208-lead enhanced quad flat pack industrial cy39030z208-125ni n208 208-lead plastic quad flat pack cy39030v144-125bbi bb144 144-lead fine pitch ball grid array cy39030z144-125bbi bb144 144-lead fine pitch ball grid array cy39030v256-125bbi bb256 256-lead fine pitch ball grid array cy39030z256-125bbi bb256 256-lead fine pitch ball grid array cy39030v256-125mbi mb256 256-lead fine pitch ball grid array cy39030z256-125mbi mb256 256-lead fine pitch ball grid array 83 cy39030v208-83ntc nt208 208-lead enhanced quad flat pack commercial cy39030z208-83nc n208 208-lead plastic quad flat pack cy39030v144-83bbc bb144 144-lead fine pitch ball grid array cy39030z144-83bbc bb144 144-lead fine pitch ball grid array cy39030v256-83bbc bb256 256-lead fine pitch ball grid array cy39030z256-83bbc bb256 256-lead fine pitch ball grid array cy39030v256-83mbc mb256 256-lead fine pitch ball grid array cy39030z256-83mbc mb256 256-lead fine pitch ball grid array cy39030v208-83nti nt208 208-lead plastic quad flat pack industrial cy39030z208-83ni n208 208-lead enhanced quad flat pack cy39030v144-83bbi bb144 144-lead fine pitch ball grid array cy39030z144-83bbi bb144 144-lead fine pitch ball grid array cy39030v256-83bbi bb256 256-lead fine pitch ball grid array cy39030z256-83bbi bb256 256-lead fine pitch ball grid array cy39030v256-83mbi mb256 256-lead fine pitch ball grid array cy39030z256-83mbi mb256 256-lead fine pitch ball grid array 39k50 222 cy39050v208-222ntc nt208 208-lead enhanced quad flat pack commercial cy39050z208-222nc n208 208-lead plastic quad flat pack cy39050v256-222bbc bb256 256-lead fine pitch ball grid array cy39050z256-222bbc bb256 256-lead fine pitch ball grid array cy39050v388-222mgc mg388 388-lead ball grid array cy39050z388-222mgc mg388 388-lead ball grid array cy39050v484-222mbc mb484 484-lead fine pitch ball grid array cy39050z484-222mbc mb484 484-lead fine pitch ball grid array 125 cy39050v208-125ntc nt208 208-lead enhanced quad flat pack cy39050z208-125nc n208 208-lead plastic quad flat pack cy39050v256-125bbc bb256 256-lead fine pitch ball grid array cy39050z256-125bbc bb256 256-lead fine pitch ball grid array cy39050v388-125mgc mg388 388-lead pitch ball grid array cy39050z388-125mgc mg388 388-lead pitch ball grid array cy39050v484-125mbc mb484 484-lead fine pitch ball grid array cy39050z484-125mbc mb484 484-lead fine pitch ball grid array delta39k part numbers [16] (ordering information) (continued) device speed (mhz) ordering code package name package type self-boot solution operating range
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 44 of 57 39k50 125 cy39050v208-125nti nt208 208-lead enhanced quad flat pack industrial cy39050z208-125ni n208 208-lead plastic quad flat pack cy39050v256-125bbi bb256 256-lead fine pitch ball grid array cy39050z256-125bbi bb256 256-lead fine pitch ball grid array cy39050v388-125mbi mg388 388-lead fine pitch ball grid array cy39050z388-125mbi mg388 388-lead fine pitch ball grid array cy39050v484-125mbi mb484 484-lead fine pitch ball grid array cy39050z484-125mbi mb484 484-lead fine pitch ball grid array 83 cy39050v208-83ntc nt208 208-lead enhanced quad flat pack commercial cy39050z208-83nc n208 208-lead plastic quad flat pack cy39050v256-83bbc bb256 256-lead fine pitch ball grid array cy39050z256-83bbc bb256 256-lead fine pitch ball grid array cy39050v388-83mgc mg388 388-lead ball grid array cy39050z388-83mgc mg388 388-lead ball grid array cy39050v484-83mbc mb484 484-lead fine pitch ball grid array cy39050z484-83mbc mb484 484-lead fine pitch ball grid array cy39050v208-83nti nt208 208-lead plastic quad flat pack industrial cy39050z208-83ni n208 208-lead enhanced quad flat pack cy39050v256-83bbi bb256 256-lead fine pitch ball grid array cy39050z256-83bbi bb256 256-lead fine pitch ball grid array cy39050v388-83mgi mg388 388-lead ball grid array cy39050z388-83mgi mg388 388-lead ball grid array cy39050v484-83mbi mb484 484-lead fine pitch ball grid array cy39050z484-83mbi mb484 484-lead fine pitch ball grid array delta39k part numbers [16] (ordering information) (continued) device speed (mhz) ordering code package name package type self-boot solution operating range
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 45 of 57 39k100 [17] 200 cy39100v208-200ntc nt208 208-lead enhanced quad flat pack commercial cy39100v256-200bbc bb256 256-lead fine pitch ball grid array cy39100v484-200bbc bb484 484-lead fine pitch ball grid array cy39100v388-200mgc mg388 388-lead ball grid array cy39100v676-200mbc mb676 676-lead fine pitch ball grid array cy39100v208a-200ntc nt208 208-lead enhanced quad flat pack cy39100v256a-200bbc bb256 256-lead fine pitch ball grid array cy39100v484a-200bbc bb484 484-lead fine pitch ball grid array cy39100v388a-200mgc mg388 388-lead ball grid array cy39100v676a-200mbc mb676 676-lead fine pitch ball grid array cy39100v208b-200ntc nt208 208-lead enhanced quad flat pack cy39100z208b-200nc n208 208-lead plastic quad flat pack cy39100v256b-200bbc bb256 256-lead fine pitch ball grid array cy39100z256b-200bbc bb256 256-lead fine pitch ball grid array cy39100v484b-200bbc bb484 484-lead fine pitch ball grid array cy39100z484b-200bbc bb484 484-lead fine pitch ball grid array cy39100v388b-200mgc mg388 388-lead ball grid array cy39100z388b-200mgc mg388 388-lead ball grid array cy39100v676b-200mbc mb676 676-lead fine pitch ball grid array cy39100z676b-200mbc mb676 676-lead fine pitch ball grid array delta39k part numbers [16] (ordering information) (continued) device speed (mhz) ordering code package name package type self-boot solution operating range
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 46 of 57 39k100 [17] 125 cy39100v208-125ntc nt208 208-lead enhanced quad flat pack commercial cy39100v256-125bbc bb256 256-lead fine pitch ball grid array cy39100v484-125bbc bb484 484-lead fine pitch ball grid array cy39100v388-125mgc mg388 388-lead ball grid array cy39100v676-125mbc mb676 676-lead fine pitch ball grid array cy39100v208a-125ntc nt208 208-lead enhanced quad flat pack cy39100v256a-125bbc bb256 256-lead fine pitch ball grid array cy39100v484a-125bbc bb484 484-lead fine pitch ball grid array cy39100v388a-125mgc mg388 388-lead ball grid array cy39100v676a-125mbc mb676 676-lead fine pitch ball grid array cy39100v208b-125ntc nt208 208-lead enhanced quad flat pack cy39100z208b-125nc n208 208-lead plastic quad flat pack cy39100v256b-125bbc bb256 256-lead fine pitch ball grid array cy39100z256b-125bbc bb256 256-lead fine pitch ball grid array cy39100v484b-125bbc bb484 484-lead fine pitch ball grid array cy39100z484b-125bbc bb484 484-lead fine pitch ball grid array cy39100v388b-125mgc mg388 388-lead ball grid array cy39100z388b-125mgc mg388 388-lead ball grid array cy39100v676b-125mbc mb676 676-lead fine pitch ball grid array cy39100z676b-125mbc mb676 676-lead fine pitch ball grid array cy39100v208b-125nti nt208 208-lead enhanced quad flat pack industrial cy39100z208b-125ni n208 208-lead plastic quad flat pack cy39100v256b-125bbi bb256 256-lead fine pitch ball grid array cy39100z256b-125bbi bb256 256-lead fine pitch ball grid array cy39100v484b-125bbi bb484 484-lead fine pitch ball grid array cy39100z484b-125bbi bb484 484-lead fine pitch ball grid array cy39100v388b-125mgi mg388 388-lead ball grid array cy39100z388b-125mgi mg388 388-lead ball grid array cy39100v676b-125mbi mb676 676-lead fine pitch ball grid array cy39100z676b-125mbi mb676 676-lead fine pitch ball grid array delta39k part numbers [16] (ordering information) (continued) device speed (mhz) ordering code package name package type self-boot solution operating range
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 47 of 57 39k100 [17] 83 cy39100v208-83ntc nt208 208-lead enhanced quad flat pack commercial cy39100v256-83bbc bb256 256-lead fine pitch ball grid array cy39100v484-83bbc bb484 484-lead fine pitch ball grid array cy39100v388-83mgc mg388 388-lead ball grid array cy39100v676-83mbc mb676 676-lead fine pitch ball grid array cy39100v208a-83ntc nt208 208-lead enhanced quad flat pack cy39100v256a-83bbc bb256 256-lead fine pitch ball grid array cy39100v484a-83bbc bb484 484-lead fine pitch ball grid array cy39100v388a-83mgc mg388 388-lead ball grid array cy39100v676a-83mbc mb676 676-lead fine pitch ball grid array cy39100v208b-83ntc nt208 208-lead enhanced quad flat pack cy39100z208b-83nc n208 208-lead plastic quad flat pack cy39100v256b-83bbc bb256 256-lead fine pitch ball grid array cy39100z256b-83bbc bb256 256-lead fine pitch ball grid array cy39100v484b-83bbc bb484 484-lead fine pitch ball grid array cy39100z484b-83bbc bb484 484-lead fine pitch ball grid array cy39100v388b-83mgc mg388 388-lead ball grid array cy39100z388b-83mgc mg388 388-lead ball grid array cy39100v676b-83mbc mb676 676-lead fine pitch ball grid array cy39100z676b-83mbc mb676 676-lead fine pitch ball grid array cy39100v208b-83nti nt208 208-lead enhanced quad flat pack industrial cy39100z208b-83ni n208 208-lead plastic quad flat pack cy39100v256b-83bbi bb256 256-lead fine pitch ball grid array cy39100z256b-83bbi bb256 256-lead fine pitch ball grid array cy39100v484b-83bbi bb484 484-lead fine pitch ball grid array cy39100z484b-83bbi bb484 484-lead fine pitch ball grid array cy39100v388b-83mgi mg388 388-lead ball grid array cy39100z388b-83mgi mg388 388-lead ball grid array cy39100v676b-83mbi mb676 676-lead fine pitch ball grid array cy39100z676b-83mbi mb676 676-lead fine pitch ball grid array delta39k part numbers [16] (ordering information) (continued) device speed (mhz) ordering code package name package type self-boot solution operating range
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 48 of 57 39k165 181 cy39165v208-181ntc nt208 208-lead enhanced quad flat pack commercial cy39165z208-181nc n208 208-lead plastic quad flat pack cy39165v484-181bbc bb484 484-lead fine pitch ball grid array cy39165z484-181bbc bb484 484-lead fine pitch ball grid array cy39165v388-181mgc mg388 388-lead ball grid array cy39165z388-181mgc mg388 388-lead ball grid array cy39165v676-181mbc mb676 676-lead fine pitch ball grid array cy39165z676-181mbc mb676 676-lead fine pitch ball grid array 125 cy39165v208-125ntc nt208 208-lead enhanced quad flat pack commercial cy39165z208-125nc n208 208-lead plastic quad flat pack cy39165v484-125bbc bb484 484-lead fine pitch ball grid array cy39165z484-125bbc bb484 484-lead fine pitch ball grid array cy39165v388-125mgc mg388 388-lead ball grid array cy39165z388-125mgc mg388 388-lead ball grid array cy39165v676-125mbc mb676 676-lead fine pitch ball grid array cy39165z676-125mbc mb676 676-lead fine pitch ball grid array cy39165v208-125nti nt208 208-lead enhanced quad flat pack industrial cy39165z208-125ni n208 208-lead plastic quad flat pack cy39165v484-125bbi bb484 484-lead fine pitch ball grid array cy39165z484-125bbi bb484 484-lead fine pitch ball grid array cy39165v388-125mgi mg388 388-lead ball grid array cy39165z388-125mgi mg388 388-lead ball grid array cy39165v676-125mbi mb676 676-lead fine pitch ball grid array cy39165z676-125mbi mb676 676-lead fine pitch ball grid array 83 cy39165v208-83ntc nt208 208-lead enhanced quad flat pack commercial cy39165z208-83nc n208 208-lead plastic quad flat pack cy39165v484-83bbc bb484 484-lead fine pitch ball grid array cy39165z484-83bbc bb484 484-lead fine pitch ball grid array cy39165v388-83mgc mg388 388-lead ball grid array cy39165z388-83mgc mg388 388-lead ball grid array cy39165v676-83mbc mb676 676-lead fine pitch ball grid array cy39165z676-83mbc mb676 676-lead fine pitch ball grid array cy39165v208-83nti nt208 208-lead enhanced quad flat pack industrial cy39165z208-83ni n208 208-lead plastic quad flat pack cy39165v484-83bbi bb484 484-lead fine pitch ball grid array cy39165z484-83bbi bb484 484-lead fine pitch ball grid array cy39165v388-83mgi mg388 388-lead ball grid array cy39165z388-83mgi mg388 388-lead ball grid array cy39165v676-83mbi mb676 676-lead fine pitch ball grid array cy39165z676-83mbi mb676 676-lead fine pitch ball grid array delta39k part numbers [16] (ordering information) (continued) device speed (mhz) ordering code package name package type self-boot solution operating range
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 49 of 57 16. for the availability of delta39kz devices (1.8v), please contact your local sales office 17. refer to the section titled ? delta39k100 revisions/errata ? on page 50 39k200 167 cy39200v208-167ntc nt208 208-lead enhanced quad flat pack commercial cy39200z208-167nc n208 208-lead plastic quad flat pack cy39200v484-167bbc bb484 484-lead fine pitch ball grid array cy39200z484-167bbc bb484 484-lead fine pitch ball grid array cy39200v388-167mgc mg388 388-lead ball grid array cy39200z388-167mgc mg388 388-lead ball grid array cy39200v676-167mbc mb676 676-lead fine pitch ball grid array CY39200Z676-167MBC mb676 676-lead fine pitch ball grid array 125 cy39200v208-125ntc nt208 208-lead enhanced quad flat pack commercial cy39200z208-125nc n208 208-lead plastic quad flat pack cy39200v484-125bbc bb484 484-lead fine pitch ball grid array cy39200z484-125bbc bb484 484-lead fine pitch ball grid array cy39200v388-125mgc mg388 388-lead ball grid array cy39200z388-125mgc mg388 388-lead ball grid array cy39200v676-125mbc mb676 676-lead fine pitch ball grid array cy39200z676-125mbc mb676 676-lead fine pitch ball grid array cy39200v208-125nti nt208 208-lead enhanced quad flat pack industrial cy39200z208-125ni n208 208-lead plastic quad flat pack cy39200v484-125bbi bb484 484-lead fine pitch ball grid array cy39200z484-125bbi bb484 484-lead fine pitch ball grid array cy39200v388-125mgi mg388 388-lead ball grid array cy39200v388-125mgi mg388 388-lead ball grid array cy39200v676-125mbi mb676 676-lead fine pitch ball grid array cy39200z676-125mbi mb676 676-lead fine pitch ball grid array 83 cy39200v208-83ntc nt208 208-lead enhanced quad flat pack commercial cy39200z208-83nc n208 208-lead plastic quad flat pack cy39200v484-83bbc bb484 484-lead fine pitch ball grid array cy39200z484-83bbc bb484 484-lead fine pitch ball grid array cy39200v388-83mgc mg388 388-lead ball grid array cy39200z388-83mgc mg388 388-lead ball grid array cy39200v676-83mbc mb676 676-lead fine pitch ball grid array cy39200z676-83mbc mb676 676-lead fine pitch ball grid array cy39200v208-83nti nt208 208-lead enhanced quad flat pack industrial cy39200z208-83ni n208 208-lead plastic quad flat pack cy39200v484-83bbi bb484 484-lead fine pitch ball grid array cy39200z484-83bbi bb484 484-lead fine pitch ball grid array cy39200v388-83mgi mg388 388-lead ball grid array cy39200z388-83mgi mg388 388-lead ball grid array cy39200v676-83mbi mb676 676-lead fine pitch ball grid array cy39200z676-83mbi mb676 676-lead fine pitch ball grid array delta39k part numbers [16] (ordering information) (continued) device speed (mhz) ordering code package name package type self-boot solution operating range
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 50 of 57 delta39k100 revisions/errata three revisions of delta39k100, in 3.3v version, are currently offered which are marked as cy39100vxxx, cy39100vxxxa and cy39100vxxxb. cy39100vxxxb devices operate exactly as specified in this datasheet. following paragraphs explain the operation of the cy39100vxxx and cy39100vxxxa parts as different from this datasheet: cy39100vxxx 1. the internal regulator takes several seconds to power down. hence, cycling the power supply (within 8 seconds) may cause a high standby current (200 ma to 1a) until the part is configured. 2. the part always configures on power-up and will reconfig- ure on high to low edge of the reconfig pin. please refer to the application note titled ? configuring delta39k/quantum38k ? at http://www.cypress.com for more details. 3. the self config instruction starts reconfiguring the cpld upon execution of the update-ir state of the jtag tap controller state machine. in cy39100vxxxb parts, self config instruction is executed upon execution of test-log- ic-reset state of the tap controller. 4. an esd failure is very unlikely. cdm esd passes 1000v. hbm esd passes 3300v with all i/o bank ? s v ccio shorted together. if v ccio s in a bank are tested separately a per- centage of parts will fail hbm esd over 500v. cy39100vxxxa 1. the part always configures on power-up and will reconfig- ure on high to low edge of the reconfig pin. please refer to the application note titled ? configuring delta39k/quantum38k ? at http://www.cypress.com for more details. 2. the self config instruction starts reconfiguring the cpld upon execution of the update-ir state of the jtag tap controller state machine. in cy39100vxxxb parts, self config instruction is executed upon execution of test-log- ic-reset state of the tap controller. 3. an esd failure is very unlikely. cdm esd passes 1000v. hbm esd passes 3300v with all i/o bank ? s v ccio shorted together. if v ccio s in a bank are tested separately a per- centage of parts will fail hbm esd over 500v.
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 51 of 57 cpld boot eeprom [18] part numbers (ordering information) device speed (mhz) ordering code package name package type operating range 1mbit 15 cy3lv010-10jc 20j 20-lead plastic leaded chip carrier commercial 10 cy3lv010-10ji 20j 20-lead plastic leaded chip carrier industrial 512kbit 15 cy3lv512-10jc 20j 20-lead plastic leaded chip carrier commercial 10 cy3lv512-10ji 20j 20-lead plastic leaded chip carrier industrial recommended cpld boot eeprom for corresponding delta39k cplds cpld device recommended boot eeprom 39k15 cy3lv256 39k30 cy3lv512 39k50 cy3lv512 39k100 cy3lv010 39k165 cy3lv020 39k200 cy3lv020 note: 18. see the data sheet titled ? cpld boot eeprom ? for detailed architectural and timing information.
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 52 of 57 package diagrams 208-lead plastic quad flatpack (pqfp) n208 51-85069-b 208-lead enhanced quad flat pack (eqfp) nt208
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 53 of 57 package diagrams (continued) 388-lead ball grid array mg388 51-85103
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 54 of 57 package diagrams (continued) 256-ball thin ball grid array (17 x 17 x 1.6 mm) bb256/mb256 51-85108-a
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 55 of 57 package diagrams (continued) 484-ball thin ball grid array (23 x 23 x 1.6 mm) bb484/mb484 51-85124
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 56 of 57 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. nobl, pim, spread aware, warp , anyvolt, self-boot, in-system reprogrammable, isr, and delta39k are trademarks of cypress semiconductor corporation. zbt is a trademark of idt. qdr is a trademark of micron, idt, and cypress semiconductor corporation. speedwave, and viewdraw are trademarks of viewlogic. mechanical drawings of 144fbga will be available soon. for package sizes and ball pitch see page 2. package diagrams (continued) 676-ball fbga (27 x 27 x 1.6 mm) bb676 51-85125
preliminary delta39k ? isr ? cpld family document #: 38-03039 rev. ** page 57 of 57 document title: delta39k ? isr ? cpld family document number: 38-03039 rev. ecn no. issue date orig. of change description of change ** 106503 05/30/01 szv change from spec #: 38-00830 to 38-03039

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